Chip Level Implementation of a Digital Radar System

Abstract

In this work, an S-Band radar system based on stretch processing technique is developed at chip level. The novelty in this work lies in providing an integrated, compact and miniaturized radar system chipset. The radar has many characteristics that ensure high performance: a wide bandwidth signal (600 MHz) that provides high resolution to distinguish between close objects, stretch processing technique that dramatically reduces the required sampling rates and relaxes the specifications of analog to digital converters, high dynamic range that allows weak signals to be detected from targets masked by high levels of clutter (such as snow and rain), multiple receiver channels that enable digital antenna beam forming at the receiver to mitigate any strong interferer, and finally operation in the S-Band (2-4 GHz) that provides high immunity against clutter in long range surveillance applications. The architecture study revealed a Super-Hetrodyne receiver and modulator architecture offered the best solution. The high order filters were pushed off chip to reduce silicon area, reduce power consumption and improve filtering results. The circuit level design focused on designing the receiver blocks. The design included a high linearity quad passive mixer, IF cascode and common source amplifiers, and a negative gm voltage controlled oscillator. The total receiver system of the radar chipset was designed and simulated at the circuit level using Cadence Virtuoso 6.0 on IBM 180 nm CMOS technology, a high dynamic range of 58 dB was achieved with a total power consumption of 0.32 W.