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dc.contributor.advisorAlbasha, Lutfi
dc.contributor.authorKashfi, Seyed Mohammad
dc.date.accessioned2016-06-07T07:13:56Z
dc.date.available2016-06-07T07:13:56Z
dc.date.issued2016-05
dc.identifier.other35.232-2016.20
dc.identifier.urihttp://hdl.handle.net/11073/8328
dc.descriptionA Master of Science thesis in Electrical Engineering by Seyed Mohammad Kashfi entitled, "Integrated Power Amplifier Design with Built-in Analog Pre-Distortion," submitted in May 2016. Thesis advisor is Dr. Lutfi Albasha. Soft and hard copy available.en_US
dc.description.abstractThe fifth generation of mobile communication (5G) is aiming for higher frequency bands, so it can be capable of delivering faster communication and higher data rate. One of the most challenging parts of power amplifier design with complex modulation scheme is to perform more efficiently at high frequency bands. Power amplifiers lay an important role in creating the possibility of total on-chip radio systems. Low voltage supplies for Complementary Metal-Oxide Semiconductor (CMOS) technology and linear power amplifier operation make the design more challenging .In this work, a 28 GHz two stages power amplifier with built-in passive analog pre-distortion is designed and simulated using global Foundries (GF) 65 nm CMOS technology. The target and aim of this design is to develop a linear lower amplifier with the maximum possible gain and optimum efficiency. This work will investigate high frequency power amplifier architectures to find out the best alternative for linearity and efficiency performance. Two stages of a common source structure have been designed and lumped elements are used for input, output and inter-stage matching. Supply voltage of 2.5 V is used for this topology. The design and simulation are based on the available models from GF. The design shows +19.84dBm of linear output power and17.1 %of power added efficiency at proposed 3GPP 5thgeneration frequencies from 27.5 GHz to 29.5 GHz)with the power gain of 20.11dB.The designs showed1.21 d Bm as input referred 1-dB compression point .Improvement of 1.46 d Bm in the output power has been achieved from built-in linearizer. Overall DC power consumption is almost 520mW and the output saturated power is 21.5dBm with an input lower range from -30 d Bm to 10 d Bm. In comparison with other designs in available literature, this power amplifier provides better and higher overall gain and linearity.en_US
dc.description.sponsorshipCollege of Engineeringen_US
dc.description.sponsorshipDepartment of Electrical Engineeringen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesMaster of Science in Electrical Engineering (MSEE)en_US
dc.relation.ispartofseriesAmerican University of Sharjah Student Worken_US
dc.subject65 nm CMOSen_US
dc.subjectPower Amplifieren_US
dc.subjectPower Added Efficiencyen_US
dc.subjectCommon Sourceen_US
dc.subjectFifth Generationen_US
dc.subjectCold Mode MOSFET Linearizeren_US
dc.subjectPre-distortionen_US
dc.subjectComplementary Metal-Oxide Semiconductor (CMOS)en_US
dc.subject.lcshPower amplifiersen_US
dc.subject.lcshMobile communication systemsen_US
dc.subject.lcshAmplifiersen_US
dc.subject.lcshRadio frequencyen_US
dc.titleIntegrated Power Amplifier Design with Built-in Analog Pre-Distortionen_US
dc.typeThesisen_US


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